1. Field of Application
The present invention relates to a circuit for executing data read and write operations in a DRAM (dynamic random access memory). In particular, the invention relates to improvements to such circuits whereby satisfactory read and write operation can be achieved even in the case of a DRAM which is formed as a large-scale integrated circuit having very high component density and which is operated with a low value of supply voltage.
2. Prior Art Technology
FIG. 1 shows an example of a prior art circuit for executing read and write operations (referred to in the following simply as a read circuit) in a DRAM that is implemented as a large-scale integrated circuit (LSI), which will be described for assistance in understanding the problems that are to be overcome by the present invention. In this example, P-type MOS and N-type MOS field effect transistors (respectively referred to in the following simply as PMOS FETs and NMOS FETs) are utilized as circuit elements. Numerals 50 denote respective pairs of bit lines, each of the bit lines being coupled to respective ones of an array of memory cells 5, and each of the bit line pairs being provided with a sense amplifier 1 which consists of an NMOS flip-flop circuit (formed of a pair of NMOS FETs connected in series between the pair of bit lines) and a sense amplifier 2 which consists of a PMOS flip-flop (formed of a pair of PMOS FETs connected between the pair of bit lines). In addition, each pair of bit lines 50 is coupled to a corresponding pair of switches 3 referred to as column switches (since the pairs of bit lines 50 successively extend along a column direction of an array of the memory cells 5), with each column switch in this example being formed of an NMOS FET, through which data can be transferred to or from the pair of bit lines during a write or read operation respectively. A word line 4 is connected to respective control electrodes of the memory cells 5 of one bit line in each pair of bit lines 50, while a word line 5 is similarly connected to respective control electrodes of the memory cells 5 of the other bit line of each pair of bit lines 50. Respective column address decoding circuits 6 are provided for each of the pairs of bit lines 50, which are connected to the gate electrodes of the column switches 3 of that pair. Each of the column address decoding circuits 6 produces a column address signal on a control line 60 at a high potential when the corresponding pair of bit lines is selected for data reading or writing to/from a memory cell
A common voltage supply line 7 is coupled to each of the common source connection points of the NMOS sense amplifier flip-flops 1, while a common voltage supply line 8 is similarly coupled to each of the PMOS sense amplifier flip-flops 2. 9 is a switch for selectively connecting the common voltage supply line 7 to ground (i.e. 0 V) potential, while a switch 9 similarly selectively connects the supply line 8 to the Vcc supply potential. The voltage supply switch 9 in this example is formed of a pair of NMOS FETs connected in parallel, and the voltage supply switch 10 is similarly formed of a pair of PMOS FETs. Control of activation of the NMOS sense amplifier flip-flops 1 by the common voltage supply line 7 (by connecting that lead to ground potential) is executed by a control signal SEN that is supplied to the voltage supply switch 9, i.e. that signal goes to an active (high) potential to activate the common voltage supply line 7. Similarly, control of activation of the PMOS sense amplifier flip-flops 2 by the common voltage supply line 8 (by connecting that lead to the Vcc supply potential) is executed by a control signal SEP supplied to the voltage supply switch 10, i.e. that signal goes to an active (low) potential to activate the common voltage supply line 8. One line of a pair of input/output data lines 11 can be selectively connected through respective column switches 3 to one line of each of the pairs of bit lines 50, while the other one of the input/output data lines 11 can similarly be connected through column switches 3 to the other line of each pair of bit lines 50. Connection of a pair of bit lines 50 to the input/output data lines 11 is controlled by the corresponding column address signal, which is applied as a switch control signal to the gate electrodes of the column switches 3 of that pair of bit lines 50.
The operation of this prior art example will be described referring to FIG. 1 in conjunction with the waveform diagrams of FIGS. 2 and 3, which illustrate a memory read cycle and write cycle respectively. A read cycle will be described first, and it will be assumed that the word line 4 is selected, i.e. that the contents of the memory cells that are coupled to the word line 4 are to be read out. The waveforms shown apply to any one of the pairs of bit lines 50 together with the sense amplifier flip-flops 1 and 2, column switches 3, and the column address decoder circuit 6 corresponding thereto. Initially, each of the bit lines is at a pre-charge potential that is equal to one half of the supply voltage value, i.e. Vcc/2, as are also the input/output data lines 11. Firstly, at time point t0, the potential of the selected word line begins to increase. Next, at the time point t1, the electrical charge that has been stored in the memory cell 5 that is to be read (i.e. the memory cell located at the intersection of the word line 4 and that pair of bit lines 50 in FIG. 1) is outputted to one of the bit lines of the pair. It is assumed in FIG. 2 that this read operation results in an increase in potential of the pair of bit lines that is connected to the memory cell, indicating that a "1" state bit was stored therein. Next, at time point t2, the common voltage supply line 7 becomes connected through the voltage supply switch 9 to ground potential (due to the control line SEN going to its active potential), so that the potential of the common voltage supply line 7 begins to fall. When that potential falls to a certain level as described hereinafter in detail, the NMOS sense amplifier flip-flop 1 becomes activated, so that amplification of the potential difference between the pair of bit lines 50 begins. More specifically, assuming that a "1" bit is read from the memory cell designated as 5' in FIG. 1, discharging of the bit line designated as 50a, through the NMOS FET designated as 1a, will begin after time point t2. The potential of that line 50a will thereby fall rapidly, i.e. the potential difference between that pair of bit lines 50 will begin to be amplified by the "pull-down" action of that NMOS sense amplifier flip-flop. Next, at time point t3, the control signal SEP acts on the voltage supply switch 10 to begin applying the supply voltage Vcc to the common voltage supply line 8, so that the potential of the common voltage supply line 8 begins to rise When that increase has reached a certain point, the PMOS sense amplifier flip-flop 2 will be activated, so that charging of the bit line designated as 50b, through the PMOS FET designated as 2a, will begin. Thus, the bit line 50a will fall towards the ground potential, and bit line 50b will rise towards the Vcc level, as a result of the amplification of the sense amplifier flip-flops 1 and 2 in combination. Next, at time point t4, the column address signal from the column address decoder circuit 6 of that pair of bit lines 50 causes the potential of the control lead 60 to increase, whereby the column switches 3 begin to connect the pair of bit lines 50 to the input/output data lines 11, i.e. to transfer the data of that pair of bit lines to the input/output data lines 11. In this example in which a "1" bit is assumed to be read out from the memory cell 5', a charging current (supplied from the PMOS FET 2a) will flow via one of the column switches 3 into the input/output data lines 11 (which have a substantially higher value of capacitance than each of the pairs of bit lines 50) from the bit line 50b, and a discharging current will similarly flow from the input/output data lines 11 via a switch 3 and the bit line 50a into the NMOS FET 1a. The data which are thus transferred from the memory cells 5 to the input/output data lines 11 are then transferred to external circuits through a data buffer (not shown in the drawing).
The operation during a write cycle will be described referring to FIG. 1 and the waveform diagram of FIG. 3. In this case, the operations which occur at time points t0, t1 and t2 are identical to those of the read cycle described hereinabove referring to FIG. 2. It will again be assumed that the word line 4 is activated. For ease of understanding, the operation of writing a "0" state bit into the memory cell 5' of the pair of bit lines 50a, 50b will be described, assuming that a "1" state bit is held in that memory cell before the write cycle begins. After the time point t3 as described hereinabove, a charging current is supplied through the PMOS FET 2a to the bit line 50b and a discharging current through the NMOS FET 1a to the bit line 50a, causing the potential difference between that pair of bit lines to be amplified. However, during a write cycle, a potential difference is established between the input/output data lines 11 prior to the time point t4 at which the column address signal of that pair of bit lines goes to the active (high) level, with the polarity of that potential difference being determined in accordance with whether a "1" or "0" bit is to be written. The respective FETs of the NMOS sense amplifier flip-flops 1, PMOS sense amplifier flip-flops 2 and column switches 3 should be configured (as described in detail hereinafter) such that when the input/output data lines 11 become connected to the pair of bit lines 50a, 50b following the time point t4. And the amplified voltage difference between the pair of bit lines is cancelled by the voltage difference between the input/output data lines 11, i.e a current flow will occur from the input/output data lines 11 into that pair of bit lines through the column switches 3, of sufficient magnitude to overcome the effects of the current supplied from the NMOS sense amplifier flip-flop 1 and PMOS sense amplifier flip-flop 2. As a result, the respective stable states of the sense amplifier flip-flops 1 and 2 of the pair of bit lines 50a, 50b are inverted, causing the bit line waveform to be inverted as shown in FIG. 3, so that the potential difference between that pair of bit lines now corresponds to a "0" bit state. Since at that time the word line 4 is still at the active level, a "0" bit is written into the memory cell 5' in this example.
However, as DRAMs have been developed which have a very high component density and high storage capacity, there is a trend towards using a lower value of supply voltage (Vcc), in order to reduce the overall power consumption and to achieve improved device reliability. For that reason, with a typical very high storage capacity DRAM, e.g. a 16 M bit DRAM, a voltage value Vcc of 3.5 V is generally used, rather than the value of 5.0 V which has been usual in previous types of DRAM. Thus, with a method of sense amplifier operation as described above in which a precharge voltage level of 1/2 Vcc is used, the operating voltages of the sense amplifier flip-flops 1 and 2 is excessively low. Specifically, with such a 1/2 Vcc sense amplifier method, the precharge voltage (i.e. the voltage of each pair of bit lines immediately prior to a read or write cycle) will be only approximately 1.65 V if the supply voltage is 3.35 V.
The problem which arises in that case will be described referring to the waveform diagram of a read cycle shown in FIG. 4, and FIG. 5 which is a conceptual diagram for illustrating gate-to-source potentials in a FET of an NMOS sense amplifier flip-flop 1 in the read cycle. It will again be assumed for ease of understanding that the description relates to the pair of bit lines 50a, 50b, memory cell 5' and related components shown in FIG. 1. In FIG. 4, the full-line portions of the pair of bit lines waveform are for the case in which a "1" bit is read out of the memory cell 5', while the broken-line portions are for the case in which a "0" bit is read. When a "1" bit is read, the potential of bit line 50b rises by the amount .DELTA.VH as shown, and thereafter the potential of the common voltage supply line 7 begins to fall from the 1/2 Vcc level towards 0 V, thereby pulling down the potential of the source electrode of FET 1a of flip-flop 1. When the difference between the gate and source of FET 1a reaches the NMOS FET threshold voltage (i.e. the voltage difference (Vg2-Vs2)=Vt2 shown in FIG. 5 becomes equal to that threshold voltage) then current begins to flow through the FET 1a, thereby pulling the potential of bit line 50a towards 0 V. Similarly, current begins to flow through transistor 2a of the sense amplifier flip-flop 2, pulling up the bit line 50b towards Vcc, so that the potential difference between the bit lines is rapidly amplified as shown.
However if a "0" bit is read from the memory cell 5', then the potential of bit line 50b will initially fall by the amount .DELTA.VL shown in FIG. 4. Thereafter, as the source potential of FET 1a is pulled down by current flowing through the common voltage supply line 7 and voltage supply switch 9, a point t11 is reached at which the potential difference between the gate and source of FET 1b reaches the NMOS FET threshold voltage (i.e. the voltage difference (Vg1-Vs1)=Vt1 shown in FIG. 5 becomes equal to that threshold voltage). The potential of the bit line 50b then begins to be pulled down towards 0 V by current flow through the FET 1b, so that amplification of the potential difference between these bit lines by the sense amplifier flip-flops 1 and 2 then begins. However, in this case the gate potential of FET 1b is initially 1/2 Vcc, (rather than 1/2 Vcc+.DELTA.VH, as occurs when a "1" state bit is read), so that as illustrated in FIG. 4 there is a delay time t.sub.d between the start of amplification of the potential difference between the bit line pair 50, for the case of a "0" bit being read, by comparison with the case of a "1" bit being read.
In a very large-scale DRAM, each common voltage supply line 7 is connected to the sense amplifier flip-flops of a large number of pairs of bit lines (e.g. typically 1024 bit lines) and so has a high value of capacitance, and due to its length, has a substantial amount of resistance. This, together with the low value of 1/2 Vcc in such a DRAM (e.g. 1.65 V), results in a low rate of fall of voltage of the common voltage supply line 7 from 1/2 Vcc towards 0 V during a write cycle, thereby increasing the amount of the delay time t.sub.d, so that the problem becomes increasingly severe as the DRAM memory capacity is increased. Moreover, in general, there will be a number of memory cells from which a "1" bit is read at the same time during a read cycle, whose sense amplifiers are supplied in common by the same common voltage supply line 7. This will result in a reduction of the rate of fall of voltage of the common voltage supply line 7 after the time point t10 in FIG. 14, since large amounts of current will then begin to flow into the common voltage supply line 7 from the NMOS sense amplifier flip-flops of the pairs of bit lines on which a "1" bit has been read. Thus if a "0" bit is read from only a small proportion of these memory cells, the problem of a delay in read-out of the "0" bits by comparison with "1" state bits will be further aggravated substantially. As a result of that delay, there is a possibility of unreliability of read operation, i.e. when a "0" state bit is read, the level of pair of bit lines potential difference amplification by the sense amplifier at the time of connection of the pair of bit lines to the input/output data lines 11 via the column switches 3 may be insufficient, as is illustrated by the broken-line waveform in FIG. 4.
One possible approach to overcoming this delay problem would be to design the FETs of the PMOS sense amplifier flip-flops 2 to have a higher value of current drive capability. However, in a conventional type of DRAM read circuit, NMOS FETs are used as the column switches 3, and it is necessary for these to have a higher level of current drive capability than the FETs of the PMOS sense amplifier flip-flops. Here, the term "current drive capability" signifies the level of current that can be transferred through the FET, (i.e. which can be increased by increasing the gate drive voltage, with a specific design of FET, or can be increased by changing the design of the FET, with a specific value of gate voltage).
The reasons making it necessary for the FETs of the column switches 3 to have a higher current drive capability than those of the flip-flops 1 are as follows. During a write cycle as described hereinabove referring to FIG. 3, prior to the time point t4 in FIG. 3, the NMOS sense amplifier ff1 of each pair of bit lines 50 is amplifying a potential difference between the bit lines whose polarity is determined in accordance with whether a "1" or "0" bit was stored in the corresponding memory cell 5. Following time point t4, if the previously stored bit in that memory cell 5 is to be inverted by the write operation, it is necessary for the drive current that is supplied through the column switches 3 to forcibly invert the respective states of the NMOS and cmos sense amplifier flip-flops 1 and 2 of that pair of bit lines. As a specific example, if a "0" state bit was previously stored in the memory cell 5', so that at time point t4 the PMOS FET 2b is connecting the pair of bit lines 50a to the common voltage supply line 8, then designating the uppermost column switch in FIG. 1 as 3a, it will now be necessary for the column switch 3a to supply a drive current of sufficient magnitude to cancel the current that can be transferred through the FET 2b. However if the PMOS FETs have a higher current drive capability than the NMOS FETs that constitute the column switches 3, then it will be difficult to rapidly and reliably execute such cancellation of the previous drive states of the sense amplifier flip-flops during a write cycle. Thus, the aforementioned delay problem cannot be overcome simply by modifying the configuration of the PMOS FETs in the sense amplifier flip-flops with respect to the NMOS fets.
If, on the other hand it were attempted to overcome this problem by increasing the current drive capability of both the NMOS FETs and PMOS FETs, then this would result in an increased level of junction capacitance of the column switches 3, since the NMOS FETs would necessarily be made of larger size. As a result, there would be a corresponding increase in the effective capacitance value of the input/output data lines 11, whose main constituents are the junction capacitances of the column switches 3. Generally, the capacitance of the input/output data lines 11 is approximately 10 times that of each of the pairs of bit lines 50, and if it were to be increased beyond that ratio, there would be a danger that the potential changes occurring on the bit lines during a read cycle (i.e. constituting data that are to be read) would be excessively attenuated by absorption in the capacitance of the input/output data lines 11, when transferred thereto through the column switches 3. Thus, reliable read operation could not be achieved, since bit line potential changes would not be transferred with sufficient speed to the input/output data lines 11.
It can thus be understood that with a prior art DRAM sense amplifier circuit, there is a basic conflict between the respective requirements for high performance during a read cycle and a write cycle. In a read cycle, it is preferable that the FETs used for the column switches 3 have a low value of junction capacitance, and hence are of small size and thus have a low level of current drive capability. In addition, during a read cycle, it is preferable that the FETs used for the sense amplifier flip-flops, including those which are of opposite type to the FETs used for the column switches 3, should have a high value of current drive capability. On the other hand, during a write cycle, the junction capacitance of the column switches 3 is not a significant factor, and it is preferable that the FETs used for the column switches 3 have a higher current drive capability than the FETs which constitute the sense amplifier flip-flop of opposite conduction type to the FETs of the column switches 3.
Thus, it is not possible to overcome the aforementioned delay problem simply by modifying the configurations of the transistors constituting the sense amplifiers and column switches.
That problem will become increasingly severe in future, as increasingly high degrees of integration are utilized to configure high memory capacity DRAMs which utilize a low value supply voltage Vcc, e.g. 3.3 V.